TY - JOUR
T1 - MALTA3
T2 - Concepts for a new radiation tolerant sensor in the TowerJazz 180 nm technology
AU - Dobrijević, Dominik
AU - Allport, Phil
AU - Asensi, Ignacio
AU - Berlea, Dumitru Vlad
AU - Bortoletto, Daniela
AU - Buttar, Craig
AU - Dachs, Florian
AU - Dao, Valerio
AU - Denizli, Haluk
AU - Flores, Leyre
AU - Gabrielli, Andrea
AU - Gonella, Laura
AU - González, Vicente
AU - LeBlanc, Matt
AU - Vázquez Núñez, Marcos
AU - Oyulmaz, Kaan
AU - Pernegger, Heinz
AU - Piro, Francesco
AU - Riedler, Petra
AU - Sandaker, Heidi
AU - Sánchez, Carlos Solans
AU - Snoeys, Walter
AU - Suligoj, Tomislav
AU - van Rijnbach, Milou
AU - Weick, Julian
AU - Worm, Steven
N1 - Publisher Copyright:
© 2022
PY - 2022/10/1
Y1 - 2022/10/1
N2 - The upgrade of the MALTA DMAPS designed in Tower 180 nm CMOS Imaging process will implement the numerous modifications, as well as front-end changes in order to boost the charge collection efficiency after the targeted fluence of 1x10151MeVneq/cm2. The effectiveness of these changes have been demonstrated in recent measurements with a small-scale Mini-MALTA demonstrator chip. Multiple changes in the digital periphery are proposed: The asynchronous address generator will be revised to provide more control over the pulse length. The Synchronization memory will be upgraded with the goal of achieving a sub-nanosecond timing resolution. Serial chip to chip data transfer will be prototyped, in order to gauge the plausibility of implementation on a future full sized chip. Apart from these changes, research of the overall sensor architecture will be discussed as well.
AB - The upgrade of the MALTA DMAPS designed in Tower 180 nm CMOS Imaging process will implement the numerous modifications, as well as front-end changes in order to boost the charge collection efficiency after the targeted fluence of 1x10151MeVneq/cm2. The effectiveness of these changes have been demonstrated in recent measurements with a small-scale Mini-MALTA demonstrator chip. Multiple changes in the digital periphery are proposed: The asynchronous address generator will be revised to provide more control over the pulse length. The Synchronization memory will be upgraded with the goal of achieving a sub-nanosecond timing resolution. Serial chip to chip data transfer will be prototyped, in order to gauge the plausibility of implementation on a future full sized chip. Apart from these changes, research of the overall sensor architecture will be discussed as well.
KW - Monolithic active pixel sensors
KW - Radiation hard electronics
KW - Silicon detectors
UR - https://www.scopus.com/pages/publications/85135513674
U2 - 10.1016/j.nima.2022.167226
DO - 10.1016/j.nima.2022.167226
M3 - Article
AN - SCOPUS:85135513674
SN - 0168-9002
VL - 1040
JO - Nuclear Inst. and Methods in Physics Research, A
JF - Nuclear Inst. and Methods in Physics Research, A
M1 - 167226
ER -