MAPPING HOMOGENEOUS GRAPHS ON LINEAR ARRAYS.

I. V. Ramakrishnan; D. S. Fussell; Abraham Silberschatz

doi:10.1109/TC.1986.1676744

MAPPING HOMOGENEOUS GRAPHS ON LINEAR ARRAYS.

I. V. Ramakrishnan
, D. S. Fussell
, Abraham Silberschatz

Computer Science

Stony Brook University

Research output: Contribution to journal › Article › peer-review

23 Scopus citations

Abstract

The authors present a formal model of linear array processors suitable for VLSI implementation, as well as graph representations of programs suitable for execution on such a model. A distinction is made between correct mapping and correct execution of such graphs on this model, and the structures of correctly mappable graphs are examined. The formalism developed is used to synthesize algorithms for this model.

Original language	English
Pages (from-to)	189-209
Number of pages	21
Journal	IEEE Transactions on Computers
Volume	C-35
Issue number	3
DOIs	https://doi.org/10.1109/TC.1986.1676744
State	Published - 1986

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10.1109/TC.1986.1676744

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title = "MAPPING HOMOGENEOUS GRAPHS ON LINEAR ARRAYS.",

abstract = "The authors present a formal model of linear array processors suitable for VLSI implementation, as well as graph representations of programs suitable for execution on such a model. A distinction is made between correct mapping and correct execution of such graphs on this model, and the structures of correctly mappable graphs are examined. The formalism developed is used to synthesize algorithms for this model.",

author = "Ramakrishnan, \{I. V.\} and Fussell, \{D. S.\} and Abraham Silberschatz",

year = "1986",

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AU - Ramakrishnan, I. V.

AU - Fussell, D. S.

AU - Silberschatz, Abraham

PY - 1986

Y1 - 1986

N2 - The authors present a formal model of linear array processors suitable for VLSI implementation, as well as graph representations of programs suitable for execution on such a model. A distinction is made between correct mapping and correct execution of such graphs on this model, and the structures of correctly mappable graphs are examined. The formalism developed is used to synthesize algorithms for this model.

AB - The authors present a formal model of linear array processors suitable for VLSI implementation, as well as graph representations of programs suitable for execution on such a model. A distinction is made between correct mapping and correct execution of such graphs on this model, and the structures of correctly mappable graphs are examined. The formalism developed is used to synthesize algorithms for this model.

UR - https://www.scopus.com/pages/publications/0022689854

U2 - 10.1109/TC.1986.1676744

DO - 10.1109/TC.1986.1676744

M3 - Article

AN - SCOPUS:0022689854

SN - 0018-9340

VL - C-35

SP - 189

EP - 209

JO - IEEE Transactions on Computers

JF - IEEE Transactions on Computers

IS - 3

ER -

MAPPING HOMOGENEOUS GRAPHS ON LINEAR ARRAYS.

Abstract

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