Mapping of partial reconfigurable data flows to xilinx fpgas

Akshay Athalye; Sangjin Hong

Mapping of partial reconfigurable data flows to xilinx fpgas

Akshay Athalye
, Sangjin Hong

Electrical Engineering

Stony Brook University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

Recently, commercially available Xilinx FPGAs have started to support partial Run Time Reconfiguration (RTR) wherein part of the FPGA can be reconfigured while the rest of the FPGA logic is functioning. However, access to the FPGA for RTR is not completely flexible and needs a systematic partitioning of the FPGA fabric into static and reconfigurable partitions within certain pretty tight constraints. Modules mapped to different partitions need to communicate using specialized macros. In this paper, we present a method for mapping a data flow requiring partial RTR to the Xilinx FPGAs. We develop a cost function that guides the mapping of nodes to these partitions by attempting to minimize the communication cost while ensuring that the required RTR is completed within certain time constraints.

Original language	English
Title of host publication	Proceedings - IEEE International SOC Conference, 2005 SOCC
Editors	D. Ha, R. Krishnamurthy, S. Kim, A. Marshall
Pages	111-112
Number of pages	2
State	Published - 2005
Event	2005 IEEE International SOC Conference - Herndon, VA, United States Duration: Sep 25 2005 → Sep 28 2005

Publication series

Name	Proceedings - IEEE International SOC Conference

Conference

Conference	2005 IEEE International SOC Conference
Country/Territory	United States
City	Herndon, VA
Period	09/25/05 → 09/28/05

Cite this

@inproceedings{7b5b378abc1244e5b18e302cd93167de,

title = "Mapping of partial reconfigurable data flows to xilinx fpgas",

abstract = "Recently, commercially available Xilinx FPGAs have started to support partial Run Time Reconfiguration (RTR) wherein part of the FPGA can be reconfigured while the rest of the FPGA logic is functioning. However, access to the FPGA for RTR is not completely flexible and needs a systematic partitioning of the FPGA fabric into static and reconfigurable partitions within certain pretty tight constraints. Modules mapped to different partitions need to communicate using specialized macros. In this paper, we present a method for mapping a data flow requiring partial RTR to the Xilinx FPGAs. We develop a cost function that guides the mapping of nodes to these partitions by attempting to minimize the communication cost while ensuring that the required RTR is completed within certain time constraints.",

author = "Akshay Athalye and Sangjin Hong",

year = "2005",

language = "English",

isbn = "0780392647",

series = "Proceedings - IEEE International SOC Conference",

pages = "111--112",

editor = "D. Ha and R. Krishnamurthy and S. Kim and A. Marshall",

booktitle = "Proceedings - IEEE International SOC Conference, 2005 SOCC",

note = "2005 IEEE International SOC Conference ; Conference date: 25-09-2005 Through 28-09-2005",

}

Mapping of partial reconfigurable data flows to xilinx fpgas. / Athalye, Akshay; Hong, Sangjin.
Proceedings - IEEE International SOC Conference, 2005 SOCC. ed. / D. Ha; R. Krishnamurthy; S. Kim; A. Marshall. 2005. p. 111-112 P.16 (Proceedings - IEEE International SOC Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Mapping of partial reconfigurable data flows to xilinx fpgas

AU - Athalye, Akshay

AU - Hong, Sangjin

PY - 2005

Y1 - 2005

N2 - Recently, commercially available Xilinx FPGAs have started to support partial Run Time Reconfiguration (RTR) wherein part of the FPGA can be reconfigured while the rest of the FPGA logic is functioning. However, access to the FPGA for RTR is not completely flexible and needs a systematic partitioning of the FPGA fabric into static and reconfigurable partitions within certain pretty tight constraints. Modules mapped to different partitions need to communicate using specialized macros. In this paper, we present a method for mapping a data flow requiring partial RTR to the Xilinx FPGAs. We develop a cost function that guides the mapping of nodes to these partitions by attempting to minimize the communication cost while ensuring that the required RTR is completed within certain time constraints.

AB - Recently, commercially available Xilinx FPGAs have started to support partial Run Time Reconfiguration (RTR) wherein part of the FPGA can be reconfigured while the rest of the FPGA logic is functioning. However, access to the FPGA for RTR is not completely flexible and needs a systematic partitioning of the FPGA fabric into static and reconfigurable partitions within certain pretty tight constraints. Modules mapped to different partitions need to communicate using specialized macros. In this paper, we present a method for mapping a data flow requiring partial RTR to the Xilinx FPGAs. We develop a cost function that guides the mapping of nodes to these partitions by attempting to minimize the communication cost while ensuring that the required RTR is completed within certain time constraints.

UR - https://www.scopus.com/pages/publications/30844454472

M3 - Conference contribution

AN - SCOPUS:30844454472

SN - 0780392647

SN - 9780780392649

T3 - Proceedings - IEEE International SOC Conference

SP - 111

EP - 112

BT - Proceedings - IEEE International SOC Conference, 2005 SOCC

A2 - Ha, D.

A2 - Krishnamurthy, R.

A2 - Kim, S.

A2 - Marshall, A.

T2 - 2005 IEEE International SOC Conference

Y2 - 25 September 2005 through 28 September 2005

ER -

Mapping of partial reconfigurable data flows to xilinx fpgas

Abstract

Publication series

Conference

Other files and links

Fingerprint

Cite this