Matrix multiplication via PGAs (programmable graph architectures)

Recently, we proposed a novel architecture for matrix operations on configurable devices. This new family of architectures is based on Cayley Graphs, hence the name, Programmable Graph Architecture (PGA). The basic idea of a PGA is to transform matrix operations into spatial graph routing problems. Such transformation allows the original operation to be implemented spatially on a configurable device, such as an FPGA (Field Programmable Gate Array) and hence increase the computational density, defined as the number of bit operations per second and micron square[1]. In this paper we examine some of the theoretical properties of Cayley graphs over the GL(N,p) group and provide a specific example to illustrate how matrix multiplication can be accomplished via Cayley graph routing.