TY - GEN
T1 - Mismatch compensation of a subthreshold CMOS current normalizer
AU - Sander, David
AU - Datta, Timir
AU - Abshire, Pamela
PY - 2010
Y1 - 2010
N2 - This paper presents a current normalization circuit with floating gate mismatch compensation. Normalization circuits are an important class of signal processing architectures, and although subthreshould MOS devices can efficiently implement these systems, their precision is often limited by fabrication mismatch. A current normalizer with outputs inversely proportional to the input signals was designed and simulated for a commercially available 0.5μm CMOS process. We show that through self-limiting floating gate mismatch compensation techniques the process induced system mismatch can be reduced by 78%.
AB - This paper presents a current normalization circuit with floating gate mismatch compensation. Normalization circuits are an important class of signal processing architectures, and although subthreshould MOS devices can efficiently implement these systems, their precision is often limited by fabrication mismatch. A current normalizer with outputs inversely proportional to the input signals was designed and simulated for a commercially available 0.5μm CMOS process. We show that through self-limiting floating gate mismatch compensation techniques the process induced system mismatch can be reduced by 78%.
UR - https://www.scopus.com/pages/publications/77955988748
U2 - 10.1109/ISCAS.2010.5537862
DO - 10.1109/ISCAS.2010.5537862
M3 - Conference contribution
AN - SCOPUS:77955988748
SN - 9781424453085
T3 - ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems
SP - 3409
EP - 3412
BT - ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
T2 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
Y2 - 30 May 2010 through 2 June 2010
ER -