Multiplier architecture power consumption characterization for low-power DSP applications

This paper presents a multiplier power consumption characterization technique used in a coefficient optimization for low-power multimedia digital signal processing. The technique accurately characterizes and models the actual power consumption of the multipliers. Based on the models, the coefficient optimization finds an optimum set of coefficient patterns. The technique is based on the relative power weight factor of each coefficient bit is defined which characterizes the power consumption of multipliers. We have developed power consumption models based on the relative power weight factors to estimate/predict power dissipation for array-type multipliers and tree-type multipliers. We have applied our methodology on FFT for obtaining the profiles of power consumption for these multiplier structures.