Near-optimal cache block placement with reactive nonuniform cache architectures

Nikos Hardavellas; Michael Ferdman; Babak Falsafi; Anastasia Ailamaki

doi:10.1109/MM.2010.22

Near-optimal cache block placement with reactive nonuniform cache architectures

Nikos Hardavellas
, Michael Ferdman
, Babak Falsafi
, Anastasia Ailamaki

Computer Science

Northwestern University
Swiss Federal Institute of Technology Lausanne

Research output: Contribution to journal › Article › peer-review

10 Scopus citations

Abstract

The growing core counts and caches of modern processors result in data access latency becoming a function of the data's physical location in the cache. Thus, the placement of cache blocks determines the cache's performance. Reactive nonuniform cache architectures (R-NUCA) achieve near-optimal cache block placement by classifying blocks online and placing data close to the cores that use them.

Original language	English
Article number	5430736
Pages (from-to)	20-28
Number of pages	9
Journal	IEEE Micro
Volume	30
Issue number	1
DOIs	https://doi.org/10.1109/MM.2010.22
State	Published - Jan 2010

Keywords

Cache memories
Data placement
Multicore
Nonuniform cache architectures
Parallel architectures

Access to Document

10.1109/MM.2010.22

Cite this

@article{f1f392d82ad64e54984a950c6f5e0d08,

title = "Near-optimal cache block placement with reactive nonuniform cache architectures",

abstract = "The growing core counts and caches of modern processors result in data access latency becoming a function of the data's physical location in the cache. Thus, the placement of cache blocks determines the cache's performance. Reactive nonuniform cache architectures (R-NUCA) achieve near-optimal cache block placement by classifying blocks online and placing data close to the cores that use them.",

keywords = "Cache memories, Data placement, Multicore, Nonuniform cache architectures, Parallel architectures",

author = "Nikos Hardavellas and Michael Ferdman and Babak Falsafi and Anastasia Ailamaki",

year = "2010",

month = jan,

doi = "10.1109/MM.2010.22",

language = "English",

volume = "30",

pages = "20--28",

journal = "IEEE Micro",

issn = "0272-1732",

number = "1",

}

TY - JOUR

T1 - Near-optimal cache block placement with reactive nonuniform cache architectures

AU - Hardavellas, Nikos

AU - Ferdman, Michael

AU - Falsafi, Babak

AU - Ailamaki, Anastasia

PY - 2010/1

Y1 - 2010/1

N2 - The growing core counts and caches of modern processors result in data access latency becoming a function of the data's physical location in the cache. Thus, the placement of cache blocks determines the cache's performance. Reactive nonuniform cache architectures (R-NUCA) achieve near-optimal cache block placement by classifying blocks online and placing data close to the cores that use them.

AB - The growing core counts and caches of modern processors result in data access latency becoming a function of the data's physical location in the cache. Thus, the placement of cache blocks determines the cache's performance. Reactive nonuniform cache architectures (R-NUCA) achieve near-optimal cache block placement by classifying blocks online and placing data close to the cores that use them.

KW - Cache memories

KW - Data placement

KW - Multicore

KW - Nonuniform cache architectures

KW - Parallel architectures

UR - https://www.scopus.com/pages/publications/77949638926

U2 - 10.1109/MM.2010.22

DO - 10.1109/MM.2010.22

M3 - Article

AN - SCOPUS:77949638926

SN - 0272-1732

VL - 30

SP - 20

EP - 28

JO - IEEE Micro

JF - IEEE Micro

IS - 1

M1 - 5430736

ER -

Near-optimal cache block placement with reactive nonuniform cache architectures

Abstract

Keywords

Access to Document

Other files and links

Fingerprint

Cite this