TY - GEN
T1 - Noise coupling due to through silicon vias (TSVs) in 3-D integrated circuits
AU - Salman, Emre
PY - 2011
Y1 - 2011
N2 - Three-dimensional (3-D) integration is a promising technology to alleviate the interconnect bottleneck by stacking multiple dies in a monolithic fashion. Both power dissipation and delay can be reduced by utilizing the third dimension where through silicon vias (TSVs) are used for vertical communication. Characteristics of switching noise that couples to a sensitive device due to a TSV are investigated in this paper. A model is developed to evaluate the noise performance of a TSV. Several noise isolation strategies are also discussed. Ignoring noise characteristics during the TSV placement process produces a poor 3-D circuit with high susceptibility to switching noise.
AB - Three-dimensional (3-D) integration is a promising technology to alleviate the interconnect bottleneck by stacking multiple dies in a monolithic fashion. Both power dissipation and delay can be reduced by utilizing the third dimension where through silicon vias (TSVs) are used for vertical communication. Characteristics of switching noise that couples to a sensitive device due to a TSV are investigated in this paper. A model is developed to evaluate the noise performance of a TSV. Several noise isolation strategies are also discussed. Ignoring noise characteristics during the TSV placement process produces a poor 3-D circuit with high susceptibility to switching noise.
UR - https://www.scopus.com/pages/publications/79960888645
U2 - 10.1109/ISCAS.2011.5937837
DO - 10.1109/ISCAS.2011.5937837
M3 - Conference contribution
AN - SCOPUS:79960888645
SN - 9781424494736
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 1411
EP - 1414
BT - 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
T2 - 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
Y2 - 15 May 2011 through 18 May 2011
ER -