Numerical analysis of hardware architecture for header compression and packet aggregation on wireless networks

This paper proposes a numerical analysis model to predict the processing delay of a hardware architecture for robust header compression and packet aggregation on wireless mesh networks. The analysis model is composed of a series of queue systems such as G/M/1, M ^[K]/M/1, M/M/1, and M/M/∞ that are one-to-one mapped into the constructed hardware components to characterize the concurrent operations and interactional relationship between encoding and decoding paths. Based on the co-simulation method which integrates NS-2 and SystemC, we show the analysis model properly approximates the processing delay of the hardware architecture. Additionally, the variation of processing delay occurring when a part of hardware components are differently configured is suitably characterized by the proposed model, and the overall mesh network behaviors is predicted by applying the numerical results into NS-2 simulations.