TY - GEN
T1 - Offline symbolic analysis to infer total store order
AU - Lee, Dongyoon
AU - Said, Mahmoud
AU - Narayanasamy, Satish
AU - Yang, Zijiang
PY - 2011
Y1 - 2011
N2 - Ability to record and replay an execution can significantly help programmers debug their programs, especially parallel programs. De-terministically replaying a multiprocessor's execution under a relaxed memory model has remained a challenging problem. This is an important problem as most modern processors only support a relaxed memory model to enable many performance critical optimizations. The most common consistency model implemented in processors is the Total Store Order (TSO). We present an efficient and low-complexity processor based solution for recording and replaying under the Total Store Order (TSO) memory model. Processor provides support for logging data fetched on cache misses. Using this information each thread can be de-terministically replayed. A TSO-compliant casual order between the shared-memory accesses executed in different threads is then inferred using an offline algorithm based on Satisfiability Modulo Theory (SMT) solver. We also discuss methods to bound the search space during offline analysis and several optimizations to reduce the offline analysis time.
AB - Ability to record and replay an execution can significantly help programmers debug their programs, especially parallel programs. De-terministically replaying a multiprocessor's execution under a relaxed memory model has remained a challenging problem. This is an important problem as most modern processors only support a relaxed memory model to enable many performance critical optimizations. The most common consistency model implemented in processors is the Total Store Order (TSO). We present an efficient and low-complexity processor based solution for recording and replaying under the Total Store Order (TSO) memory model. Processor provides support for logging data fetched on cache misses. Using this information each thread can be de-terministically replayed. A TSO-compliant casual order between the shared-memory accesses executed in different threads is then inferred using an offline algorithm based on Satisfiability Modulo Theory (SMT) solver. We also discuss methods to bound the search space during offline analysis and several optimizations to reduce the offline analysis time.
UR - https://www.scopus.com/pages/publications/79955927767
U2 - 10.1109/HPCA.2011.5749743
DO - 10.1109/HPCA.2011.5749743
M3 - Conference contribution
AN - SCOPUS:79955927767
SN - 9781424494323
T3 - Proceedings - International Symposium on High-Performance Computer Architecture
SP - 357
EP - 368
BT - Proceedings - 17th International Symposium on High-Performance Computer Architecture, HPCA 2011
T2 - 17th International Symposium on High-Performance Computer Architecture, HPCA 2011
Y2 - 12 February 2011 through 16 February 2011
ER -