TY - GEN
T1 - On-chip hybrid regulator topology for portable SoCs with near-threshold operation
AU - Park, Yongwan
AU - Salman, Emre
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/7/29
Y1 - 2016/7/29
N2 - A novel hybrid regulator topology is proposed to alleviate the weaknesses of existing hybrid topologies. Contrary to the dominant existing practice, a switched-capacitor converter and a resistorless LDO operate in a parallel fashion to supply current and regulate the output voltage. The proposed design targets a fully integrated regulator without using any inductors and resistors. The primary emphasis is on maximizing power efficiency while maintaining sufficient regulation capability (with ripple voltage less than 5% of the output voltage) and power density. Simulation results in 45 nm technology demonstrate a power efficiency of approximately 85% at 100 mA load current with an input and output voltage of, respectively, 1.15 V and 0.5 V. The worst case transient response time is under 20 ns when the load current varies from 65 mA to 130 mA. The worst case ripple is 22 mV while achieving a power density of 0.5 W/mm2. These results outperform existing studies and demonstrate the applicability of the proposed regulator to portable SoCs.
AB - A novel hybrid regulator topology is proposed to alleviate the weaknesses of existing hybrid topologies. Contrary to the dominant existing practice, a switched-capacitor converter and a resistorless LDO operate in a parallel fashion to supply current and regulate the output voltage. The proposed design targets a fully integrated regulator without using any inductors and resistors. The primary emphasis is on maximizing power efficiency while maintaining sufficient regulation capability (with ripple voltage less than 5% of the output voltage) and power density. Simulation results in 45 nm technology demonstrate a power efficiency of approximately 85% at 100 mA load current with an input and output voltage of, respectively, 1.15 V and 0.5 V. The worst case transient response time is under 20 ns when the load current varies from 65 mA to 130 mA. The worst case ripple is 22 mV while achieving a power density of 0.5 W/mm2. These results outperform existing studies and demonstrate the applicability of the proposed regulator to portable SoCs.
UR - https://www.scopus.com/pages/publications/84983452489
U2 - 10.1109/ISCAS.2016.7527358
DO - 10.1109/ISCAS.2016.7527358
M3 - Conference contribution
AN - SCOPUS:84983452489
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 786
EP - 789
BT - ISCAS 2016 - IEEE International Symposium on Circuits and Systems
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016
Y2 - 22 May 2016 through 25 May 2016
ER -