TY - GEN
T1 - On-line histogram equalization for flash ADC
AU - Wong, Yanyi L.
AU - Cohen, Marc
AU - Abshire, Pamela
PY - 2007
Y1 - 2007
N2 - We present theory, design and measurement results for an on-line histogram equalization algorithm implemented on a 750MS/s 6b flash analog to digital converter in standard 0.35/im CMOS. The user simply turns on "training mode" for a few seconds, while the algorithm automatically adjusts comparator levels to match the observed input signal distribution. This results in signal conversion with equal probability for each of the output codewords. The new architecture is an extension of a flash ADC incorporating an adaptive floating gate comparator and control circuits for automatic programming of the reference levels. Experiments show output codes with at least 5.9 bits entropy for ramp, sine and Gaussian random signals after adaptation. Uniform programming produces 5.7 ENOB for input frequencies up to 200MHz and maximum DNL and INL of 0.24 LSB and 0.79 LSB at Nyquist rate, while equalization produces 5.3 ENOB up to 600MHz.
AB - We present theory, design and measurement results for an on-line histogram equalization algorithm implemented on a 750MS/s 6b flash analog to digital converter in standard 0.35/im CMOS. The user simply turns on "training mode" for a few seconds, while the algorithm automatically adjusts comparator levels to match the observed input signal distribution. This results in signal conversion with equal probability for each of the output codewords. The new architecture is an extension of a flash ADC incorporating an adaptive floating gate comparator and control circuits for automatic programming of the reference levels. Experiments show output codes with at least 5.9 bits entropy for ramp, sine and Gaussian random signals after adaptation. Uniform programming produces 5.7 ENOB for input frequencies up to 200MHz and maximum DNL and INL of 0.24 LSB and 0.79 LSB at Nyquist rate, while equalization produces 5.3 ENOB up to 600MHz.
UR - https://www.scopus.com/pages/publications/34548861784
U2 - 10.1109/iscas.2007.378531
DO - 10.1109/iscas.2007.378531
M3 - Conference contribution
AN - SCOPUS:34548861784
SN - 1424409209
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 3598
EP - 3601
BT - 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007
Y2 - 27 May 2007 through 30 May 2007
ER -