TY - GEN
T1 - Optimal submodule capacitor sizing for modular multilevel converters with common mode voltage injection and circulating current control
AU - Ke, Ziwei
AU - Pan, Jianyu
AU - Potty, Karun
AU - Perdikakis, William
AU - Shanmuganaatham, Arvind
AU - Sabbagh, Muneer Al
AU - Zhang, Julia
AU - Luo, Fang
AU - Wang, Jin
AU - Xu, Longya
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/11/3
Y1 - 2017/11/3
N2 - Modular multilevel converters (MMCs), with the filterless and transformer-less features, are considered as a promising topology for high-efficiency medium voltage (MV) high voltage (HV) drive systems. However, at low frequencies (< 30 Hz), a large current ripple flowing through the capacitors of each submodule will cause significant capacitor voltage fluctuation. This paper proposes an optimal submodule capacitor selection based on the common mode voltage injection. The proposed sizing model includes two functions: A) accurately estimating the capacitor voltage ripple based on the drive system parameters; and b) identifying the minimum capacitance of the submodule capacitors based on the allowed maximum capacitor voltage fluctuations. Simulation and hardware-in-The-loop (HIL) test results show that the error between the actual and estimated values of the voltage fluctuation is within 3% using the proposed model.
AB - Modular multilevel converters (MMCs), with the filterless and transformer-less features, are considered as a promising topology for high-efficiency medium voltage (MV) high voltage (HV) drive systems. However, at low frequencies (< 30 Hz), a large current ripple flowing through the capacitors of each submodule will cause significant capacitor voltage fluctuation. This paper proposes an optimal submodule capacitor selection based on the common mode voltage injection. The proposed sizing model includes two functions: A) accurately estimating the capacitor voltage ripple based on the drive system parameters; and b) identifying the minimum capacitance of the submodule capacitors based on the allowed maximum capacitor voltage fluctuations. Simulation and hardware-in-The-loop (HIL) test results show that the error between the actual and estimated values of the voltage fluctuation is within 3% using the proposed model.
KW - Capacitor sizing
KW - MMC
KW - Motor drives
KW - Ripple reduction technique
UR - https://www.scopus.com/pages/publications/85041438163
U2 - 10.1109/ECCE.2017.8096013
DO - 10.1109/ECCE.2017.8096013
M3 - Conference contribution
AN - SCOPUS:85041438163
T3 - 2017 IEEE Energy Conversion Congress and Exposition, ECCE 2017
SP - 1802
EP - 1808
BT - 2017 IEEE Energy Conversion Congress and Exposition, ECCE 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 9th Annual IEEE Energy Conversion Congress and Exposition, ECCE 2017
Y2 - 1 October 2017 through 5 October 2017
ER -