OSIRIS: Automated synthesis of flat and hierarchical bus architectures for deep submicron systems on chip

Nattawut Thepayasuwan; Alex Doboli

doi:10.1109/ISVLSI.2004.1339550

OSIRIS: Automated synthesis of flat and hierarchical bus architectures for deep submicron systems on chip

Nattawut Thepayasuwan
, Alex Doboli

Electrical Engineering

Stony Brook University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

This paper presents a bus architecture (BA) synthesis algorithm for designing the communication sub-system of an SoC. The novelty is that a potential variable at physical level, namely, total bus length is comtemplated during the synthesis process. The algorithm generates both flat and hierarchical bus architecture using performance parameters, i.e., bus length, topology complexity, potential for communica-tion conflicts over time. BA synthesis results for a network processor is discussed.

Original language	English
Title of host publication	Proceedings - IEEE Computer Society Annual Symposium on VLSI
Subtitle of host publication	Emerging Trends in VLSI Systems Design
Editors	A. Smailagic, M. Bayoumi
Pages	264-265
Number of pages	2
DOIs	https://doi.org/10.1109/ISVLSI.2004.1339550
State	Published - 2004
Event	Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design - Lafayette, LA, United States Duration: Feb 19 2004 → Feb 20 2004

Publication series

Name	Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design

Conference

Conference	Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design
Country/Territory	United States
City	Lafayette, LA
Period	02/19/04 → 02/20/04

Access to Document

10.1109/ISVLSI.2004.1339550

Cite this

Thepayasuwan, N., & Doboli, A. (2004). OSIRIS: Automated synthesis of flat and hierarchical bus architectures for deep submicron systems on chip. In A. Smailagic, & M. Bayoumi (Eds.), Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (pp. 264-265). (Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design). https://doi.org/10.1109/ISVLSI.2004.1339550

Thepayasuwan, Nattawut ; Doboli, Alex. / OSIRIS : Automated synthesis of flat and hierarchical bus architectures for deep submicron systems on chip. Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design. editor / A. Smailagic ; M. Bayoumi. 2004. pp. 264-265 (Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design).

@inproceedings{50e94c17b0e14e2f96ab6abaaf4428b8,

title = "OSIRIS: Automated synthesis of flat and hierarchical bus architectures for deep submicron systems on chip",

abstract = "This paper presents a bus architecture (BA) synthesis algorithm for designing the communication sub-system of an SoC. The novelty is that a potential variable at physical level, namely, total bus length is comtemplated during the synthesis process. The algorithm generates both flat and hierarchical bus architecture using performance parameters, i.e., bus length, topology complexity, potential for communica-tion conflicts over time. BA synthesis results for a network processor is discussed.",

author = "Nattawut Thepayasuwan and Alex Doboli",

year = "2004",

doi = "10.1109/ISVLSI.2004.1339550",

language = "English",

isbn = "0769520979",

series = "Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design",

pages = "264--265",

editor = "A. Smailagic and M. Bayoumi",

booktitle = "Proceedings - IEEE Computer Society Annual Symposium on VLSI",

note = "Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design ; Conference date: 19-02-2004 Through 20-02-2004",

}

Thepayasuwan, N & Doboli, A 2004, OSIRIS: Automated synthesis of flat and hierarchical bus architectures for deep submicron systems on chip. in A Smailagic & M Bayoumi (eds), Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design. Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design, pp. 264-265, Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design, Lafayette, LA, United States, 02/19/04. https://doi.org/10.1109/ISVLSI.2004.1339550

OSIRIS: Automated synthesis of flat and hierarchical bus architectures for deep submicron systems on chip. / Thepayasuwan, Nattawut; Doboli, Alex.
Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design. ed. / A. Smailagic; M. Bayoumi. 2004. p. 264-265 (Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - OSIRIS

T2 - Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design

AU - Thepayasuwan, Nattawut

AU - Doboli, Alex

PY - 2004

Y1 - 2004

N2 - This paper presents a bus architecture (BA) synthesis algorithm for designing the communication sub-system of an SoC. The novelty is that a potential variable at physical level, namely, total bus length is comtemplated during the synthesis process. The algorithm generates both flat and hierarchical bus architecture using performance parameters, i.e., bus length, topology complexity, potential for communica-tion conflicts over time. BA synthesis results for a network processor is discussed.

AB - This paper presents a bus architecture (BA) synthesis algorithm for designing the communication sub-system of an SoC. The novelty is that a potential variable at physical level, namely, total bus length is comtemplated during the synthesis process. The algorithm generates both flat and hierarchical bus architecture using performance parameters, i.e., bus length, topology complexity, potential for communica-tion conflicts over time. BA synthesis results for a network processor is discussed.

UR - https://www.scopus.com/pages/publications/4544236617

U2 - 10.1109/ISVLSI.2004.1339550

DO - 10.1109/ISVLSI.2004.1339550

M3 - Conference contribution

AN - SCOPUS:4544236617

SN - 0769520979

SN - 9780769520971

T3 - Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design

SP - 264

EP - 265

BT - Proceedings - IEEE Computer Society Annual Symposium on VLSI

A2 - Smailagic, A.

A2 - Bayoumi, M.

Y2 - 19 February 2004 through 20 February 2004

ER -

Thepayasuwan N, Doboli A. OSIRIS: Automated synthesis of flat and hierarchical bus architectures for deep submicron systems on chip. In Smailagic A, Bayoumi M, editors, Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design. 2004. p. 264-265. (Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design). doi: 10.1109/ISVLSI.2004.1339550

OSIRIS: Automated synthesis of flat and hierarchical bus architectures for deep submicron systems on chip

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this