TY - GEN
T1 - Overcoming resource underutilization in spatial CNN accelerators
AU - Shen, Yongming
AU - Ferdman, Michael
AU - Milder, Peter
N1 - Publisher Copyright:
© 2016 EPFL.
PY - 2016/9/26
Y1 - 2016/9/26
N2 - Convolutional neural networks (CNNs) are revolutionizing a variety of machine learning tasks, but they present significant computational challenges. Recently, FPGA-based accelerators have been proposed to improve the speed and efficiency of CNNs. Current approaches construct an accelerator optimized to maximize the overall throughput of iteratively computing the CNN layers. However, this approach leads to dynamic resource underutilization because the same accelerator is used to compute CNN layers of radically varying dimensions. We present a new CNN accelerator design that improves the dynamic resource utilization. Using the same FPGA resources, we build multiple accelerators, each specialized for specific CNN layers. Our design achieves 1.3× higher throughput than the state of the art when evaluating the convolutional layers of the popular AlexNet CNN on a Xilinx Virtex-7 FPGA.
AB - Convolutional neural networks (CNNs) are revolutionizing a variety of machine learning tasks, but they present significant computational challenges. Recently, FPGA-based accelerators have been proposed to improve the speed and efficiency of CNNs. Current approaches construct an accelerator optimized to maximize the overall throughput of iteratively computing the CNN layers. However, this approach leads to dynamic resource underutilization because the same accelerator is used to compute CNN layers of radically varying dimensions. We present a new CNN accelerator design that improves the dynamic resource utilization. Using the same FPGA resources, we build multiple accelerators, each specialized for specific CNN layers. Our design achieves 1.3× higher throughput than the state of the art when evaluating the convolutional layers of the popular AlexNet CNN on a Xilinx Virtex-7 FPGA.
UR - https://www.scopus.com/pages/publications/84994895402
U2 - 10.1109/FPL.2016.7577315
DO - 10.1109/FPL.2016.7577315
M3 - Conference contribution
AN - SCOPUS:84994895402
T3 - FPL 2016 - 26th International Conference on Field-Programmable Logic and Applications
BT - FPL 2016 - 26th International Conference on Field-Programmable Logic and Applications
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 26th International Conference on Field-Programmable Logic and Applications, FPL 2016
Y2 - 29 August 2016 through 2 September 2016
ER -