Power and signal integrity challenges in 3D systems-on-chip

A significant physical design challenge in both high-performance 3D integrated circuits and lowpower 3D systems-on-chip is to guarantee system-wide power and signal integrity. This chapter provides an overview of these challenges with emphasis on through silicon via (TSV)-based 3D ICs. Different TSV types and their implications to power/signal integrity are first discussed. In the next section, power distribution methodology for a nine-plane processor-memory stack is described. Different decoupling capacitor topologies are also investigated for power-gated 3D ICs. The following section focuses on TSV-to-transistor noise coupling as an important signal integrity issue. A compact model is also proposed to achieve efficient noise coupling analysis in 3D ICs. Finally, a case study is described to analyze signal integrity in a 3D integrated SoC with application to bioelectronics.