Power-complexity analysis of pipelined VLSI FFT architectures for low energy wireless communication applications

Sangjin Hong; Suhwan Kim; Marios C. Papaefthymiou; Wayne E. Stark

Power-complexity analysis of pipelined VLSI FFT architectures for low energy wireless communication applications

Sangjin Hong
, Suhwan Kim
, Marios C. Papaefthymiou
, Wayne E. Stark

Electrical Engineering

University of Michigan, Ann Arbor

Research output: Contribution to conference › Paper › peer-review

10 Scopus citations

Abstract

Large fixed-throughput fast Fourier transform (FFT) modules are used in multi-carrier spread spectrum receiver design for demodulation and synchronization. The power dissipation of an FFT module depends highly on the number of processing units and their interconnect topology. This paper analyzes the energy dissipation and complexity of a pipelined parallel FFT architecture. Optimum design choices are presented for the degree of spatial parallelism and temporal multiplexing. Simulation results are obtained using EPOCH and HSPICE with 0.35 μm standard CMOS technology.

Original language	English
Pages	313-316
Number of pages	4
State	Published - 1999
Event	1999 IEEE 42nd Midwest Symposium on Circuits and Sistems - Las Cruces, NM, USA Duration: Aug 8 1999 → Aug 11 1999

Conference

Conference	1999 IEEE 42nd Midwest Symposium on Circuits and Sistems
City	Las Cruces, NM, USA
Period	08/8/99 → 08/11/99

Cite this

@conference{7d48aba51f3347da89dcec9f24eb7851,

title = "Power-complexity analysis of pipelined VLSI FFT architectures for low energy wireless communication applications",

abstract = "Large fixed-throughput fast Fourier transform (FFT) modules are used in multi-carrier spread spectrum receiver design for demodulation and synchronization. The power dissipation of an FFT module depends highly on the number of processing units and their interconnect topology. This paper analyzes the energy dissipation and complexity of a pipelined parallel FFT architecture. Optimum design choices are presented for the degree of spatial parallelism and temporal multiplexing. Simulation results are obtained using EPOCH and HSPICE with 0.35 μm standard CMOS technology.",

author = "Sangjin Hong and Suhwan Kim and Papaefthymiou, \{Marios C.\} and Stark, \{Wayne E.\}",

year = "1999",

language = "English",

pages = "313--316",

note = "1999 IEEE 42nd Midwest Symposium on Circuits and Sistems ; Conference date: 08-08-1999 Through 11-08-1999",

}

TY - CONF

T1 - Power-complexity analysis of pipelined VLSI FFT architectures for low energy wireless communication applications

AU - Hong, Sangjin

AU - Kim, Suhwan

AU - Papaefthymiou, Marios C.

AU - Stark, Wayne E.

PY - 1999

Y1 - 1999

N2 - Large fixed-throughput fast Fourier transform (FFT) modules are used in multi-carrier spread spectrum receiver design for demodulation and synchronization. The power dissipation of an FFT module depends highly on the number of processing units and their interconnect topology. This paper analyzes the energy dissipation and complexity of a pipelined parallel FFT architecture. Optimum design choices are presented for the degree of spatial parallelism and temporal multiplexing. Simulation results are obtained using EPOCH and HSPICE with 0.35 μm standard CMOS technology.

AB - Large fixed-throughput fast Fourier transform (FFT) modules are used in multi-carrier spread spectrum receiver design for demodulation and synchronization. The power dissipation of an FFT module depends highly on the number of processing units and their interconnect topology. This paper analyzes the energy dissipation and complexity of a pipelined parallel FFT architecture. Optimum design choices are presented for the degree of spatial parallelism and temporal multiplexing. Simulation results are obtained using EPOCH and HSPICE with 0.35 μm standard CMOS technology.

UR - https://www.scopus.com/pages/publications/0033292714

M3 - Paper

AN - SCOPUS:0033292714

SP - 313

EP - 316

T2 - 1999 IEEE 42nd Midwest Symposium on Circuits and Sistems

Y2 - 8 August 1999 through 11 August 1999

ER -

Power-complexity analysis of pipelined VLSI FFT architectures for low energy wireless communication applications

Abstract

Conference

Other files and links

Fingerprint

Cite this