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Power consumption vs. decoding performance relationship of VLSI decoders for low energy wireless communication system design

  • University of Michigan, Ann Arbor

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

8 Scopus citations

Abstract

In this paper we investigate power consumption and performance relationships of low complexity VLSI decoders. The study incorporates various representative of decoding algorithms such as turbo-code, block-code, Hadamard code, and convolutional-code. For each of these decoders, its decoding performance and power consumption are estimated from actual implementation. For the turbo-code, a low complexity decoder architecture is presented. The decoder circuit complexities are analyzed in terms of size and power based on 0.6-μm CMOS standard cell technology. This study provides very valuable insights into system design trade-offs involving not only low-power VLSI decoders design but for low energy wireless mobile communication systems.

Original languageEnglish
Title of host publicationProceedings of ICECS 1999 - 6th IEEE International Conference on Electronics, Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1593-1596
Number of pages4
ISBN (Electronic)0780356829
DOIs
StatePublished - 1999
Event6th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1999 - Pafos, Cyprus
Duration: Sep 5 1999Sep 8 1999

Publication series

NameProceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Volume3

Conference

Conference6th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1999
Country/TerritoryCyprus
CityPafos
Period09/5/9909/8/99

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