Power-efficient, reliable microprocessor architectures: Modeling and design methods

Pradip Bose; Alper Buyuktosunoglu; Chen Yong Cher; John A. Darringer; Meeta S. Gupta; Hendrik Hamann; Hans Jacobson; Prabhakar N. Kudva; Eren Kursun; Niti Madan; Indira Nair; Jude A. Rivers; Jeonghee Shin; Alan J. Weger; Victor Zyuban

doi:10.1145/1785481.1785551

Power-efficient, reliable microprocessor architectures: Modeling and design methods

Pradip Bose
, Alper Buyuktosunoglu
, Chen Yong Cher
, John A. Darringer
, Meeta S. Gupta
, Hendrik Hamann
, Hans Jacobson
, Prabhakar N. Kudva
, Eren Kursun
, Niti Madan
, Indira Nair
, Jude A. Rivers
, Jeonghee Shin
, Alan J. Weger
, Victor Zyuban

Office of the Dean SOMAS

IBM

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

Next generation system designs are challenged by multiple "walls": among them, the inter-related impediments offered by power dissipation limits and reliability are particularly difficult ones that all current chip/system design teams are grappling with. In this paper, we first describe the attendant challenges in integrated (multi-dimensional) pre-silicon modeling and the solution approaches being pursued. Later, we focus on leading edge solutions for power, thermal and failure-rate mitigation that have been proposed in our R&D work over the past decade.

Original language	English
Title of host publication	GLSVLSI'10 - Proceedings of the Great Lakes Symposium on VLSI 2010
Pages	299-304
Number of pages	6
DOIs	https://doi.org/10.1145/1785481.1785551
State	Published - 2010
Event	20th Great Lakes Symposium on VLSI, GLSVLSI 2010 - Providence, RI, United States Duration: May 16 2010 → May 18 2010

Publication series

Name	Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Conference

Conference	20th Great Lakes Symposium on VLSI, GLSVLSI 2010
Country/Territory	United States
City	Providence, RI
Period	05/16/10 → 05/18/10

Keywords

power-efficient design
pre-silicon modeling
reliable operation

Access to Document

10.1145/1785481.1785551

Cite this

Bose, P., Buyuktosunoglu, A., Cher, C. Y., Darringer, J. A., Gupta, M. S., Hamann, H., Jacobson, H., Kudva, P. N., Kursun, E., Madan, N., Nair, I., Rivers, J. A., Shin, J., Weger, A. J., & Zyuban, V. (2010). Power-efficient, reliable microprocessor architectures: Modeling and design methods. In GLSVLSI'10 - Proceedings of the Great Lakes Symposium on VLSI 2010 (pp. 299-304). (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI). https://doi.org/10.1145/1785481.1785551

@inproceedings{793da2c6ce974860ad22dd6b559b5e67,

title = "Power-efficient, reliable microprocessor architectures: Modeling and design methods",

abstract = "Next generation system designs are challenged by multiple {"}walls{"}: among them, the inter-related impediments offered by power dissipation limits and reliability are particularly difficult ones that all current chip/system design teams are grappling with. In this paper, we first describe the attendant challenges in integrated (multi-dimensional) pre-silicon modeling and the solution approaches being pursued. Later, we focus on leading edge solutions for power, thermal and failure-rate mitigation that have been proposed in our R\&D work over the past decade.",

keywords = "power-efficient design, pre-silicon modeling, reliable operation",

author = "Pradip Bose and Alper Buyuktosunoglu and Cher, \{Chen Yong\} and Darringer, \{John A.\} and Gupta, \{Meeta S.\} and Hendrik Hamann and Hans Jacobson and Kudva, \{Prabhakar N.\} and Eren Kursun and Niti Madan and Indira Nair and Rivers, \{Jude A.\} and Jeonghee Shin and Weger, \{Alan J.\} and Victor Zyuban",

year = "2010",

doi = "10.1145/1785481.1785551",

language = "English",

isbn = "9781450300124",

series = "Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI",

pages = "299--304",

booktitle = "GLSVLSI'10 - Proceedings of the Great Lakes Symposium on VLSI 2010",

note = "20th Great Lakes Symposium on VLSI, GLSVLSI 2010 ; Conference date: 16-05-2010 Through 18-05-2010",

}

Bose, P, Buyuktosunoglu, A, Cher, CY, Darringer, JA, Gupta, MS, Hamann, H, Jacobson, H, Kudva, PN, Kursun, E, Madan, N, Nair, I, Rivers, JA, Shin, J, Weger, AJ & Zyuban, V 2010, Power-efficient, reliable microprocessor architectures: Modeling and design methods. in GLSVLSI'10 - Proceedings of the Great Lakes Symposium on VLSI 2010. Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, pp. 299-304, 20th Great Lakes Symposium on VLSI, GLSVLSI 2010, Providence, RI, United States, 05/16/10. https://doi.org/10.1145/1785481.1785551

Power-efficient, reliable microprocessor architectures: Modeling and design methods. / Bose, Pradip; Buyuktosunoglu, Alper; Cher, Chen Yong et al.
GLSVLSI'10 - Proceedings of the Great Lakes Symposium on VLSI 2010. 2010. p. 299-304 (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Power-efficient, reliable microprocessor architectures

T2 - 20th Great Lakes Symposium on VLSI, GLSVLSI 2010

AU - Bose, Pradip

AU - Buyuktosunoglu, Alper

AU - Cher, Chen Yong

AU - Darringer, John A.

AU - Gupta, Meeta S.

AU - Hamann, Hendrik

AU - Jacobson, Hans

AU - Kudva, Prabhakar N.

AU - Kursun, Eren

AU - Madan, Niti

AU - Nair, Indira

AU - Rivers, Jude A.

AU - Shin, Jeonghee

AU - Weger, Alan J.

AU - Zyuban, Victor

PY - 2010

Y1 - 2010

N2 - Next generation system designs are challenged by multiple "walls": among them, the inter-related impediments offered by power dissipation limits and reliability are particularly difficult ones that all current chip/system design teams are grappling with. In this paper, we first describe the attendant challenges in integrated (multi-dimensional) pre-silicon modeling and the solution approaches being pursued. Later, we focus on leading edge solutions for power, thermal and failure-rate mitigation that have been proposed in our R&D work over the past decade.

AB - Next generation system designs are challenged by multiple "walls": among them, the inter-related impediments offered by power dissipation limits and reliability are particularly difficult ones that all current chip/system design teams are grappling with. In this paper, we first describe the attendant challenges in integrated (multi-dimensional) pre-silicon modeling and the solution approaches being pursued. Later, we focus on leading edge solutions for power, thermal and failure-rate mitigation that have been proposed in our R&D work over the past decade.

KW - power-efficient design

KW - pre-silicon modeling

KW - reliable operation

UR - https://www.scopus.com/pages/publications/77954523021

U2 - 10.1145/1785481.1785551

DO - 10.1145/1785481.1785551

M3 - Conference contribution

AN - SCOPUS:77954523021

SN - 9781450300124

T3 - Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

SP - 299

EP - 304

BT - GLSVLSI'10 - Proceedings of the Great Lakes Symposium on VLSI 2010

Y2 - 16 May 2010 through 18 May 2010

ER -

Power-efficient, reliable microprocessor architectures: Modeling and design methods

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Keywords

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