TY - GEN
T1 - Power gating topologies in TSV based 3D integrated circuits
AU - Wang, Hailang
AU - Salman, Emre
PY - 2013
Y1 - 2013
N2 - Two topologies are proposed at the physical level to achieve reliable power gating in through silicon via (TSV) based three-dimensional (3D) integrated circuits (ICs). The proposed lumped and distributed power gating topologies address the unique differences among distinct TSV fabrication methods such as via-first, via-middle, and via-last, while achieving, on average, 85% reduction in the leakage power. Related tradeoffs among power supply noise, power gating noise, physical area, and turn-on time are also investigated.
AB - Two topologies are proposed at the physical level to achieve reliable power gating in through silicon via (TSV) based three-dimensional (3D) integrated circuits (ICs). The proposed lumped and distributed power gating topologies address the unique differences among distinct TSV fabrication methods such as via-first, via-middle, and via-last, while achieving, on average, 85% reduction in the leakage power. Related tradeoffs among power supply noise, power gating noise, physical area, and turn-on time are also investigated.
KW - 3d ic
KW - noise
KW - power gating
KW - tsv
UR - https://www.scopus.com/pages/publications/84878180270
U2 - 10.1145/2483028.2483125
DO - 10.1145/2483028.2483125
M3 - Conference contribution
AN - SCOPUS:84878180270
SN - 9781450319027
T3 - Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
SP - 327
EP - 328
BT - GLSVLSI 2013 - Proceedings of the ACM International Conference of the Great Lakes Symposium on VLSI
T2 - 23rd ACM International Conference of the Great Lakes Symposium on VLSI, GLSVLSI 2013
Y2 - 2 May 2013 through 3 May 2013
ER -