Progress with physically and logically reversible superconducting digital circuits

We continue to develop a new Superconductor Flux Logic (SFL) family based on nSQUID gates with fundamentally low energy dissipation and the ability to operate in irreversible and reversible modes. Prospective computers utilizing the new gates can keep conventional logically irreversible architectures. In this case the energy dissipation is limited by fundamental thermodynamic laws and could be as low as a few k_BTs per logic operation. Highly exotic and less practical logically and physically reversible circuit architectures are more attractive for us because they enable a reduction of the specific energy dissipation well below the thermodynamic threshold k_BT ln 2. The reversible option is of interest to us because we can then experimentally demonstrate that all technical mechanisms of the energy dissipation could be cut below the fundamental thermodynamic limit. In other words, we like to set the energy dissipation record for all conventional digital technologies that (if measured in k_BT) is about one million times below the best figures achieved in commercially available semiconductor circuits. Besides, we believe that diving below the thermodynamic threshold would have impressive scientific and philosophical impacts. In the paper we introduce a new timing belt clocking scheme and present new circuits. While we still work with test circuits, some of them contain two 8-stage shift registers, one with direct and the other with inverted outputs. The energy dissipation per nSQUID gate per bit measured at 4 K temperature is already below the thermodynamic threshold. We are confident that we passed through the critical phase of the project and we simply need more time to make more sophisticated circuits. The extremely low energy dissipation converts our circuits into a natural candidate to support circuitry for any sensors operating at milli-Kelvin temperatures.