Reconfigurable embedded MAC core design for low-power coarse-grain FPGA

Sangjin Hong; Shu Shin Chin

doi:10.1049/el:20030364

Reconfigurable embedded MAC core design for low-power coarse-grain FPGA

Sangjin Hong
, Shu Shin Chin

Electrical Engineering

Stony Brook University

Research output: Contribution to journal › Article › peer-review

3 Scopus citations

Abstract

A reconfigurable multiplier design for low-power field programmable gate arrays (FPGAs) is presented. Power consumption reduction is achieved through varying the depth of pipeline of the multiplier. The multiplier incorporates a capability of configuring itself dynamically, thus, is suitable for FPGA type of design.

Original language	English
Pages (from-to)	606-608
Number of pages	3
Journal	Electronics Letters
Volume	39
Issue number	7
DOIs	https://doi.org/10.1049/el:20030364
State	Published - Apr 3 2003

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title = "Reconfigurable embedded MAC core design for low-power coarse-grain FPGA",

abstract = "A reconfigurable multiplier design for low-power field programmable gate arrays (FPGAs) is presented. Power consumption reduction is achieved through varying the depth of pipeline of the multiplier. The multiplier incorporates a capability of configuring itself dynamically, thus, is suitable for FPGA type of design.",

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AB - A reconfigurable multiplier design for low-power field programmable gate arrays (FPGAs) is presented. Power consumption reduction is achieved through varying the depth of pipeline of the multiplier. The multiplier incorporates a capability of configuring itself dynamically, thus, is suitable for FPGA type of design.

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Reconfigurable embedded MAC core design for low-power coarse-grain FPGA

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