Reconfigurable particle filter design using dataflow structure translation

Sangjin Hong; Xiaoyao Liang; Petar M. Djurić

doi:10.1109/SIPS.2005.1579887

Reconfigurable particle filter design using dataflow structure translation

Sangjin Hong
, Xiaoyao Liang
, Petar M. Djurić

Electrical Engineering

Stony Brook University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Scopus citations

Abstract

This paper presents reconfigurable particle filter design, which provides a capability of selecting a single particle filter from multiple particle filter realizations. The execution of the design is based on block level pipelining where data transfer between processing blocks is effectively controlled by autonomous controllers. With a simple switching mechanism that allows transformation of dataflow structure in addition to autonomous buffer controller, any desired particle filter can be performed. Two target particle filters, based on SIRF and GPF, are realized. From the execution characteristics obtained from the FPGA implementation, overall controller structure is derived according to the methodology and verified using Verilog and SystemC.

Original language	English
Title of host publication	2004 IEEE Workshop on Signal Processing Systems Design and Implementation, Proceedings
Pages	325-330
Number of pages	6
DOIs	https://doi.org/10.1109/SIPS.2005.1579887
State	Published - 2004
Event	2004 IEEE Workshop on Signal Processing Systems Design and Implementation, Proceedings - Austin, TX, United States Duration: Oct 13 2004 → Oct 15 2004

Publication series

Name	IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
ISSN (Print)	1520-6130

Conference

Conference	2004 IEEE Workshop on Signal Processing Systems Design and Implementation, Proceedings
Country/Territory	United States
City	Austin, TX
Period	10/13/04 → 10/15/04

Access to Document

10.1109/SIPS.2005.1579887

Cite this

@inproceedings{407e3e49f55b4c14912f9fd547edeffb,

title = "Reconfigurable particle filter design using dataflow structure translation",

abstract = "This paper presents reconfigurable particle filter design, which provides a capability of selecting a single particle filter from multiple particle filter realizations. The execution of the design is based on block level pipelining where data transfer between processing blocks is effectively controlled by autonomous controllers. With a simple switching mechanism that allows transformation of dataflow structure in addition to autonomous buffer controller, any desired particle filter can be performed. Two target particle filters, based on SIRF and GPF, are realized. From the execution characteristics obtained from the FPGA implementation, overall controller structure is derived according to the methodology and verified using Verilog and SystemC.",

author = "Sangjin Hong and Xiaoyao Liang and Djuri{\'c}, \{Petar M.\}",

year = "2004",

doi = "10.1109/SIPS.2005.1579887",

language = "English",

isbn = "0780393333",

series = "IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation",

pages = "325--330",

booktitle = "2004 IEEE Workshop on Signal Processing Systems Design and Implementation, Proceedings",

note = "2004 IEEE Workshop on Signal Processing Systems Design and Implementation, Proceedings ; Conference date: 13-10-2004 Through 15-10-2004",

}

Hong, S, Liang, X & Djurić, PM 2004, Reconfigurable particle filter design using dataflow structure translation. in 2004 IEEE Workshop on Signal Processing Systems Design and Implementation, Proceedings. IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation, pp. 325-330, 2004 IEEE Workshop on Signal Processing Systems Design and Implementation, Proceedings, Austin, TX, United States, 10/13/04. https://doi.org/10.1109/SIPS.2005.1579887

Reconfigurable particle filter design using dataflow structure translation. / Hong, Sangjin; Liang, Xiaoyao; Djurić, Petar M.
2004 IEEE Workshop on Signal Processing Systems Design and Implementation, Proceedings. 2004. p. 325-330 (IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

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AU - Hong, Sangjin

AU - Liang, Xiaoyao

AU - Djurić, Petar M.

PY - 2004

Y1 - 2004

N2 - This paper presents reconfigurable particle filter design, which provides a capability of selecting a single particle filter from multiple particle filter realizations. The execution of the design is based on block level pipelining where data transfer between processing blocks is effectively controlled by autonomous controllers. With a simple switching mechanism that allows transformation of dataflow structure in addition to autonomous buffer controller, any desired particle filter can be performed. Two target particle filters, based on SIRF and GPF, are realized. From the execution characteristics obtained from the FPGA implementation, overall controller structure is derived according to the methodology and verified using Verilog and SystemC.

AB - This paper presents reconfigurable particle filter design, which provides a capability of selecting a single particle filter from multiple particle filter realizations. The execution of the design is based on block level pipelining where data transfer between processing blocks is effectively controlled by autonomous controllers. With a simple switching mechanism that allows transformation of dataflow structure in addition to autonomous buffer controller, any desired particle filter can be performed. Two target particle filters, based on SIRF and GPF, are realized. From the execution characteristics obtained from the FPGA implementation, overall controller structure is derived according to the methodology and verified using Verilog and SystemC.

UR - https://www.scopus.com/pages/publications/17044398565

U2 - 10.1109/SIPS.2005.1579887

DO - 10.1109/SIPS.2005.1579887

M3 - Conference contribution

AN - SCOPUS:17044398565

SN - 0780393333

T3 - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

SP - 325

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BT - 2004 IEEE Workshop on Signal Processing Systems Design and Implementation, Proceedings

T2 - 2004 IEEE Workshop on Signal Processing Systems Design and Implementation, Proceedings

Y2 - 13 October 2004 through 15 October 2004

ER -

Reconfigurable particle filter design using dataflow structure translation

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