Scheduling of conditional process graphs for the synthesis of embedded systems

Petru Eles; Krzysztof Kuchcinski; Zebo Peng; Alexa Doboli; Paul Pop

doi:10.1109/DATE.1998.655847

Scheduling of conditional process graphs for the synthesis of embedded systems

Petru Eles
, Krzysztof Kuchcinski
, Zebo Peng
, Alexa Doboli
, Paul Pop

Electrical Engineering

Linköping University
Politehnica University of Timisoara

Research output: Contribution to journal › Conference article › peer-review

92 Scopus citations

Abstract

We present an approach to process scheduling based on an abstract graph representation which captures both data-flow and the flow of control. Target architectures consist of several processors, ASICs and shared buses. We have developed a heuristic which generates a schedule table so that the worst case delay is minimized. Several experiments demonstrate the efficiency of the approach.

Original language	English
Article number	655847
Pages (from-to)	132-138
Number of pages	7
Journal	Proceedings -Design, Automation and Test in Europe, DATE
DOIs	https://doi.org/10.1109/DATE.1998.655847
State	Published - 1998
Event	Design, Automation and Test in Europe, DATE 1998 - Paris, France Duration: Feb 23 1998 → Feb 26 1998

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title = "Scheduling of conditional process graphs for the synthesis of embedded systems",

abstract = "We present an approach to process scheduling based on an abstract graph representation which captures both data-flow and the flow of control. Target architectures consist of several processors, ASICs and shared buses. We have developed a heuristic which generates a schedule table so that the worst case delay is minimized. Several experiments demonstrate the efficiency of the approach.",

author = "Petru Eles and Krzysztof Kuchcinski and Zebo Peng and Alexa Doboli and Paul Pop",

year = "1998",

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AU - Eles, Petru

AU - Kuchcinski, Krzysztof

AU - Peng, Zebo

AU - Doboli, Alexa

AU - Pop, Paul

PY - 1998

Y1 - 1998

N2 - We present an approach to process scheduling based on an abstract graph representation which captures both data-flow and the flow of control. Target architectures consist of several processors, ASICs and shared buses. We have developed a heuristic which generates a schedule table so that the worst case delay is minimized. Several experiments demonstrate the efficiency of the approach.

AB - We present an approach to process scheduling based on an abstract graph representation which captures both data-flow and the flow of control. Target architectures consist of several processors, ASICs and shared buses. We have developed a heuristic which generates a schedule table so that the worst case delay is minimized. Several experiments demonstrate the efficiency of the approach.

UR - https://www.scopus.com/pages/publications/0043196791

U2 - 10.1109/DATE.1998.655847

DO - 10.1109/DATE.1998.655847

M3 - Conference article

AN - SCOPUS:0043196791

SN - 1530-1591

SP - 132

EP - 138

JO - Proceedings -Design, Automation and Test in Europe, DATE

JF - Proceedings -Design, Automation and Test in Europe, DATE

M1 - 655847

T2 - Design, Automation and Test in Europe, DATE 1998

Y2 - 23 February 1998 through 26 February 1998

ER -

Scheduling of conditional process graphs for the synthesis of embedded systems

Abstract

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