Scheduling of conditional process graphs for the synthesis of embedded systems

Petru Eles; Krzysztof Kuchcinski; Zebo Peng; Alexa Doboli; Paul Pop

doi:10.1007/978-1-4020-6488-3_2

Scheduling of conditional process graphs for the synthesis of embedded systems

Petru Eles
, Krzysztof Kuchcinski
, Zebo Peng
, Alexa Doboli
, Paul Pop

Electrical Engineering

Linköping University
Politehnica University of Timisoara

Research output: Chapter in Book/Report/Conference proceeding › Chapter › peer-review

5 Scopus citations

Abstract

We present an approach to process scheduling based on an abstract graph representation which captures both data-flow and the flow of control. Target architectures consist of several processors, ASICs and shared busses. We have developed a heuristic which generates a schedule table so that the worst case delay is minimized. Several experiments demonstrate the efficiency of the approach.

Original language	English
Title of host publication	Design, Automation, and Test in Europe
Subtitle of host publication	The Most Influential Papers of 10 Years Date
Publisher	Springer Netherlands
Pages	15-29
Number of pages	15
ISBN (Print)	9781402064876
DOIs	https://doi.org/10.1007/978-1-4020-6488-3_2
State	Published - 2008

Access to Document

10.1007/978-1-4020-6488-3_2

Cite this

@inbook{9b7b849000a1457ead4985c60cdddb7a,

title = "Scheduling of conditional process graphs for the synthesis of embedded systems",

abstract = "We present an approach to process scheduling based on an abstract graph representation which captures both data-flow and the flow of control. Target architectures consist of several processors, ASICs and shared busses. We have developed a heuristic which generates a schedule table so that the worst case delay is minimized. Several experiments demonstrate the efficiency of the approach.",

author = "Petru Eles and Krzysztof Kuchcinski and Zebo Peng and Alexa Doboli and Paul Pop",

year = "2008",

doi = "10.1007/978-1-4020-6488-3\_2",

language = "English",

isbn = "9781402064876",

pages = "15--29",

booktitle = "Design, Automation, and Test in Europe",

publisher = "Springer Netherlands",

}

TY - CHAP

T1 - Scheduling of conditional process graphs for the synthesis of embedded systems

AU - Eles, Petru

AU - Kuchcinski, Krzysztof

AU - Peng, Zebo

AU - Doboli, Alexa

AU - Pop, Paul

PY - 2008

Y1 - 2008

N2 - We present an approach to process scheduling based on an abstract graph representation which captures both data-flow and the flow of control. Target architectures consist of several processors, ASICs and shared busses. We have developed a heuristic which generates a schedule table so that the worst case delay is minimized. Several experiments demonstrate the efficiency of the approach.

AB - We present an approach to process scheduling based on an abstract graph representation which captures both data-flow and the flow of control. Target architectures consist of several processors, ASICs and shared busses. We have developed a heuristic which generates a schedule table so that the worst case delay is minimized. Several experiments demonstrate the efficiency of the approach.

UR - https://www.scopus.com/pages/publications/84895359585

U2 - 10.1007/978-1-4020-6488-3_2

DO - 10.1007/978-1-4020-6488-3_2

M3 - Chapter

AN - SCOPUS:84895359585

SN - 9781402064876

SP - 15

EP - 29

BT - Design, Automation, and Test in Europe

PB - Springer Netherlands

ER -

Scheduling of conditional process graphs for the synthesis of embedded systems

Abstract

Access to Document

Other files and links

Fingerprint

Cite this