Signal shaping at interface of wireless power harvesting and AC computational logic

The wirelessly powered adiabatic logic has introduced significant power savings in the design of the computational logic. We explore energy-efficient interfacing of one of the most efficient adiabatic logic families, pass-transistor adiabatic logic (PAL), with RF harvested signal. The interface circuit, signal shaper, transforms the bipolar sinusoidal input voltage to non-negative unipolar sinusoidal output that serves as the power clock signal for PAL. A theoretical analysis of the operation of the signal shaper is presented and verified using simulations in 65 nm CMOS technology. The designed shaper, when interfaced with 8-bit multiplier implemented using PAL, demonstrates the settling time of a few clock periods and high power conversion efficiency as high as 90%.