TY - GEN
T1 - Split Inductor Design Considerations for Split-Phase Three-Phase Inverter
AU - Mirza, Abdul Basit
AU - Vala, Sama Salehi
AU - Bhansali, Gaurav
AU - Narayanasamy, Balaji
AU - Luo, Fang
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - Two-Level Split-Phase (2L-SP) topology has emerged as a promising candidate for Wide Band Gap (WBG)-based Two-Level (2L) three-phase inverters. 2L-SP comprises P and N-cells whose mid-points are connected through split inductors. Compared with standard 2L, 2L-SP provides better immunity to crosstalk, lower switching loss, and conducted EMI emissions, which is favorable for WBG devices. However, these performance metrics depend on the value of split inductance. Further, split inductors experience a current spike during the switching transition. Although increasing split inductance is shown to improve the metrics and suppress the current spikes, an approach for optimal selection of split inductance is yet to be devised. This paper presents an analysis for design considerations, based on current spikes, for split inductor sizing. At first, a simplified model is derived and validated on a 75 kVA SiC-based hardware prototype. This is followed by an analysis of proposed model in the context of split inductor sizing.
AB - Two-Level Split-Phase (2L-SP) topology has emerged as a promising candidate for Wide Band Gap (WBG)-based Two-Level (2L) three-phase inverters. 2L-SP comprises P and N-cells whose mid-points are connected through split inductors. Compared with standard 2L, 2L-SP provides better immunity to crosstalk, lower switching loss, and conducted EMI emissions, which is favorable for WBG devices. However, these performance metrics depend on the value of split inductance. Further, split inductors experience a current spike during the switching transition. Although increasing split inductance is shown to improve the metrics and suppress the current spikes, an approach for optimal selection of split inductance is yet to be devised. This paper presents an analysis for design considerations, based on current spikes, for split inductor sizing. At first, a simplified model is derived and validated on a 75 kVA SiC-based hardware prototype. This is followed by an analysis of proposed model in the context of split inductor sizing.
KW - Current spikes
KW - split-inductor sizing
KW - split-phase topology (2L-SP)
KW - two-level inverter (2L)
KW - wide band gap (WBG)
UR - https://www.scopus.com/pages/publications/85182949897
U2 - 10.1109/ECCE53617.2023.10362470
DO - 10.1109/ECCE53617.2023.10362470
M3 - Conference contribution
AN - SCOPUS:85182949897
T3 - 2023 IEEE Energy Conversion Congress and Exposition, ECCE 2023
SP - 2377
EP - 2382
BT - 2023 IEEE Energy Conversion Congress and Exposition, ECCE 2023
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2023 IEEE Energy Conversion Congress and Exposition, ECCE 2023
Y2 - 29 October 2023 through 2 November 2023
ER -