Supercompilers for massively parallel architectures

Barbara Chapman; Mario Pantano; Hans Zima

doi:10.1109/AISPAS.1995.401323

Supercompilers for massively parallel architectures

Barbara Chapman
, Mario Pantano
, Hans Zima

Computer Science

University of Vienna

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

We describe the design of a compilation system, which translates Fortran programs automatically into explicitly parallel programs for a massively parallel architecture. Such a compiler must automatically generate data distributions and derive program transformation strategies based on a combination of heuristics and analysis features. Programs are subjected to an iterative tuning process, involving three major components: a restructuring system, a performance analysts subsystem, and a parallelization support environment. Many of the components in this environment have already been implemented in the framework of the Vienna Fortran compilation system.

Original language	English
Title of host publication	Proceedings - 1st Aizu International Symposium on Parallel Algorithms/Architecture Synthesis, AISPAS 1995
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	315-322
Number of pages	8
ISBN (Electronic)	081867038X, 9780818670381
DOIs	https://doi.org/10.1109/AISPAS.1995.401323
State	Published - 1995
Event	1st Aizu International Symposium on Parallel Algorithms/Architecture Synthesis, AISPAS 1995 - Aizu-Wakamatsu, Fukushima, Japan Duration: Mar 15 1995 → Mar 17 1995

Publication series

Name	Proceedings - 1st Aizu International Symposium on Parallel Algorithms/Architecture Synthesis, AISPAS 1995

Conference

Conference	1st Aizu International Symposium on Parallel Algorithms/Architecture Synthesis, AISPAS 1995
Country/Territory	Japan
City	Aizu-Wakamatsu, Fukushima
Period	03/15/95 → 03/17/95

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10.1109/AISPAS.1995.401323

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Chapman, B., Pantano, M., & Zima, H. (1995). Supercompilers for massively parallel architectures. In Proceedings - 1st Aizu International Symposium on Parallel Algorithms/Architecture Synthesis, AISPAS 1995 (pp. 315-322). Article 401323 (Proceedings - 1st Aizu International Symposium on Parallel Algorithms/Architecture Synthesis, AISPAS 1995). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/AISPAS.1995.401323

Chapman, Barbara ; Pantano, Mario ; Zima, Hans. / Supercompilers for massively parallel architectures. Proceedings - 1st Aizu International Symposium on Parallel Algorithms/Architecture Synthesis, AISPAS 1995. Institute of Electrical and Electronics Engineers Inc., 1995. pp. 315-322 (Proceedings - 1st Aizu International Symposium on Parallel Algorithms/Architecture Synthesis, AISPAS 1995).

@inproceedings{34a498e64b454ea7b5fea406801bffd3,

title = "Supercompilers for massively parallel architectures",

abstract = "We describe the design of a compilation system, which translates Fortran programs automatically into explicitly parallel programs for a massively parallel architecture. Such a compiler must automatically generate data distributions and derive program transformation strategies based on a combination of heuristics and analysis features. Programs are subjected to an iterative tuning process, involving three major components: a restructuring system, a performance analysts subsystem, and a parallelization support environment. Many of the components in this environment have already been implemented in the framework of the Vienna Fortran compilation system.",

author = "Barbara Chapman and Mario Pantano and Hans Zima",

note = "Publisher Copyright: {\textcopyright} 1995 IEEE.; 1st Aizu International Symposium on Parallel Algorithms/Architecture Synthesis, AISPAS 1995 ; Conference date: 15-03-1995 Through 17-03-1995",

year = "1995",

doi = "10.1109/AISPAS.1995.401323",

language = "English",

series = "Proceedings - 1st Aizu International Symposium on Parallel Algorithms/Architecture Synthesis, AISPAS 1995",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "315--322",

booktitle = "Proceedings - 1st Aizu International Symposium on Parallel Algorithms/Architecture Synthesis, AISPAS 1995",

}

Chapman, B, Pantano, M & Zima, H 1995, Supercompilers for massively parallel architectures. in Proceedings - 1st Aizu International Symposium on Parallel Algorithms/Architecture Synthesis, AISPAS 1995., 401323, Proceedings - 1st Aizu International Symposium on Parallel Algorithms/Architecture Synthesis, AISPAS 1995, Institute of Electrical and Electronics Engineers Inc., pp. 315-322, 1st Aizu International Symposium on Parallel Algorithms/Architecture Synthesis, AISPAS 1995, Aizu-Wakamatsu, Fukushima, Japan, 03/15/95. https://doi.org/10.1109/AISPAS.1995.401323

Supercompilers for massively parallel architectures. / Chapman, Barbara; Pantano, Mario; Zima, Hans.
Proceedings - 1st Aizu International Symposium on Parallel Algorithms/Architecture Synthesis, AISPAS 1995. Institute of Electrical and Electronics Engineers Inc., 1995. p. 315-322 401323 (Proceedings - 1st Aizu International Symposium on Parallel Algorithms/Architecture Synthesis, AISPAS 1995).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Pantano, Mario

AU - Zima, Hans

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N2 - We describe the design of a compilation system, which translates Fortran programs automatically into explicitly parallel programs for a massively parallel architecture. Such a compiler must automatically generate data distributions and derive program transformation strategies based on a combination of heuristics and analysis features. Programs are subjected to an iterative tuning process, involving three major components: a restructuring system, a performance analysts subsystem, and a parallelization support environment. Many of the components in this environment have already been implemented in the framework of the Vienna Fortran compilation system.

AB - We describe the design of a compilation system, which translates Fortran programs automatically into explicitly parallel programs for a massively parallel architecture. Such a compiler must automatically generate data distributions and derive program transformation strategies based on a combination of heuristics and analysis features. Programs are subjected to an iterative tuning process, involving three major components: a restructuring system, a performance analysts subsystem, and a parallelization support environment. Many of the components in this environment have already been implemented in the framework of the Vienna Fortran compilation system.

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T3 - Proceedings - 1st Aizu International Symposium on Parallel Algorithms/Architecture Synthesis, AISPAS 1995

SP - 315

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BT - Proceedings - 1st Aizu International Symposium on Parallel Algorithms/Architecture Synthesis, AISPAS 1995

PB - Institute of Electrical and Electronics Engineers Inc.

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Chapman B, Pantano M, Zima H. Supercompilers for massively parallel architectures. In Proceedings - 1st Aizu International Symposium on Parallel Algorithms/Architecture Synthesis, AISPAS 1995. Institute of Electrical and Electronics Engineers Inc. 1995. p. 315-322. 401323. (Proceedings - 1st Aizu International Symposium on Parallel Algorithms/Architecture Synthesis, AISPAS 1995). doi: 10.1109/AISPAS.1995.401323

Supercompilers for massively parallel architectures

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