Synthesis of continuous-time filters and analog to digital converters by integrated constraint transformation, floorplanning and routing

Hua Tang; Hui Zhang; Alex Doboli

doi:10.1145/764808.764861

Synthesis of continuous-time filters and analog to digital converters by integrated constraint transformation, floorplanning and routing

Hua Tang
, Hui Zhang
, Alex Doboli

Electrical Engineering

Stony Brook University

Research output: Contribution to journal › Conference article › peer-review

7 Scopus citations

Abstract

This paper describes a layout-aware analog synthesis methodology. The methodology includes parameter exploration and classification, parameter domain pruning and sampling, and identification of parameter dependencies. The optimization process executes a combined constraint transformation, floorplanning and global routing. The paper presents results for a high frequency continuous-time filter, and two ΣΔ ADCs. Compared to similar work, the methodology is more flexible in handling new designs, and more tolerant in accommodating layout parasitics.

Original language	English
Pages (from-to)	207-210
Number of pages	4
Journal	Proceedings of the IEEE Great Lakes Symposium on VLSI
DOIs	https://doi.org/10.1145/764808.764861
State	Published - 2003
Event	Proceedings of the 2003 ACM Great Lakes Symposium on VLSI - Washington, DC, United States Duration: Apr 28 2003 → Apr 29 2003

Keywords

Continuous-time filter
Synthesis
ΣΔ modulator

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10.1145/764808.764861

Cite this

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title = "Synthesis of continuous-time filters and analog to digital converters by integrated constraint transformation, floorplanning and routing",

abstract = "This paper describes a layout-aware analog synthesis methodology. The methodology includes parameter exploration and classification, parameter domain pruning and sampling, and identification of parameter dependencies. The optimization process executes a combined constraint transformation, floorplanning and global routing. The paper presents results for a high frequency continuous-time filter, and two ΣΔ ADCs. Compared to similar work, the methodology is more flexible in handling new designs, and more tolerant in accommodating layout parasitics.",

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AU - Tang, Hua

AU - Zhang, Hui

AU - Doboli, Alex

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N2 - This paper describes a layout-aware analog synthesis methodology. The methodology includes parameter exploration and classification, parameter domain pruning and sampling, and identification of parameter dependencies. The optimization process executes a combined constraint transformation, floorplanning and global routing. The paper presents results for a high frequency continuous-time filter, and two ΣΔ ADCs. Compared to similar work, the methodology is more flexible in handling new designs, and more tolerant in accommodating layout parasitics.

AB - This paper describes a layout-aware analog synthesis methodology. The methodology includes parameter exploration and classification, parameter domain pruning and sampling, and identification of parameter dependencies. The optimization process executes a combined constraint transformation, floorplanning and global routing. The paper presents results for a high frequency continuous-time filter, and two ΣΔ ADCs. Compared to similar work, the methodology is more flexible in handling new designs, and more tolerant in accommodating layout parasitics.

KW - Continuous-time filter

KW - Synthesis

KW - ΣΔ modulator

UR - https://www.scopus.com/pages/publications/0038714051

U2 - 10.1145/764808.764861

DO - 10.1145/764808.764861

M3 - Conference article

AN - SCOPUS:0038714051

SN - 1066-1395

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EP - 210

JO - Proceedings of the IEEE Great Lakes Symposium on VLSI

JF - Proceedings of the IEEE Great Lakes Symposium on VLSI

T2 - Proceedings of the 2003 ACM Great Lakes Symposium on VLSI

Y2 - 28 April 2003 through 29 April 2003

ER -

Synthesis of continuous-time filters and analog to digital converters by integrated constraint transformation, floorplanning and routing

Abstract

Keywords

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