TY - GEN
T1 - Temperature-limited microprocessors
T2 - 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems, VLSID'07
AU - Hamann, Hendrik F.
AU - Weger, Alan
AU - Lacey, James
AU - Hu, Zhigang
AU - Bose, Pradip
AU - Cohen, Erwin
AU - Wakil, Jamil
PY - 2007
Y1 - 2007
N2 - The details of the power distribution of state of the art CMOS chips (e.g., local regions of high power (or hotspots), which disproportionally drive up junction temperatures) can have a severe impact on reliability, manufacturing yield and chip performances. In this paper we discuss the results of a recently developed technique (Spatially-resolved imaging of microprocessor power (SIMP)), which can measure power and temperature distributions of high power chips (e.g., microprocessors) under full operating conditions. Specifically, we present detailed microprocessor power distributions for different workloads with and without power/thermal management. The data yields a more comprehensive understanding of the relationships between hotspots and the respective designs, layouts, floorplans, microarchitectures and thermal/power management schemes, which is discussed in detail.
AB - The details of the power distribution of state of the art CMOS chips (e.g., local regions of high power (or hotspots), which disproportionally drive up junction temperatures) can have a severe impact on reliability, manufacturing yield and chip performances. In this paper we discuss the results of a recently developed technique (Spatially-resolved imaging of microprocessor power (SIMP)), which can measure power and temperature distributions of high power chips (e.g., microprocessors) under full operating conditions. Specifically, we present detailed microprocessor power distributions for different workloads with and without power/thermal management. The data yields a more comprehensive understanding of the relationships between hotspots and the respective designs, layouts, floorplans, microarchitectures and thermal/power management schemes, which is discussed in detail.
UR - https://www.scopus.com/pages/publications/48349125704
U2 - 10.1109/VLSID.2007.154
DO - 10.1109/VLSID.2007.154
M3 - Conference contribution
AN - SCOPUS:48349125704
SN - 0769527620
SN - 9780769527628
T3 - Proceedings of the IEEE International Conference on VLSI Design
SP - 427
EP - 432
BT - Proceedings - 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems
Y2 - 6 January 2007 through 10 January 2007
ER -