The RatCAP Front-End ASIC

We report on the design and characterization of a new ASIC for the RatCAP, a head-mounted miniature PET scanner intended for neurological and behavioral studies of an awake rat. The ASIC is composed of 32 channels, each consisting of a charge sensitive preamplifier, a 5-bit programmable gain in the pole-zero network, a 3^rd order bipolar semi-Gaussian shaper (peaking time of 80 ns), and a timing and energy discriminator. The energy discriminator in each channel is used to arm the zero-crossing discriminator and can be programmed to use either a low energy threshold or an energy gating window. A 32-to-1 serial encoder is embedded to multiplex into a single output the timing information and channel address of every event. Finally, LVDS I/O were integrated on chip to minimize the digital noise on the read-out PCB. The ASIC was realized in the TSMC 0.18 μm technology, has a size of 3.3 mm × 4.5 mm and a power consumption of 117 mW. The gate length of the N-channel MOSFET input device of the charge sensitive preamplifier was increased to minimize 1/f noise. This led to a factor ∼ 1,5 improvement of the ENC with respect to the first version of the ASIC [1]. An ENC of 650 e-rms was measured with the APD biased at the input. In order to predict the achievable timing resolution, a model was derived to estimate the photon noise contribution to the timing resolution. Measurements were performed to validate the model, which agreed within 12%. The coincidence timing resolution between two typical LSO-APD-ASIC modules was measured using a ⁶⁸Ge source. Applying a threshold at 420 keV, a timing resolution of 6.7 ns FWHM was measured. An energy resolution of 18.7% FWHM at 511 keV was measured for a ⁶⁸Ge source.