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Thermal-aware task scheduling at the system software level

  • Jeonghwan Choi
  • , Chen Yong Cher
  • , Hubertus Franke
  • , Hendrik Hamann
  • , Alan Weger
  • , Pradip Bose
  • IBM

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

140 Scopus citations

Abstract

Power-related issues have become important considerations in current generation microprocessor design. One of these issues is that of elevated on-chip temperatures. This has an adverse effect on cooling cost and, if not addressed suitably, on chip reliability. In this paper we investigate the general trade-offs between temporal and spatial hot spot mitigation schemes and thermal time constants, workload variations and microprocessor power distributions. By leveraging spatial and temporal heat slacks, our schemes enable lowering of on-chip unit temperatures by changing the workload in a timely manner with Operating System(OS) and existing hardware support.

Original languageEnglish
Title of host publicationISLPED'07
Subtitle of host publicationProceedings of the 2007 International Symposium on Low Power Electronics and Design
Pages213-218
Number of pages6
DOIs
StatePublished - 2007
EventISLPED'07: 2007 International Symposium on Low Power Electronics and Design - Portland, OR, United States
Duration: Aug 27 2007Aug 29 2007

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)1533-4678

Conference

ConferenceISLPED'07: 2007 International Symposium on Low Power Electronics and Design
Country/TerritoryUnited States
CityPortland, OR
Period08/27/0708/29/07

Keywords

  • System level power management
  • Thermal management

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