@inproceedings{e2cf977023f64b6fa0a1a1155dd53ef3,
title = "Toward Partial Discharge Reduction by Corner Correction in Power Module Layouts",
abstract = "As spacing between traces in power modules is reduced to meet increasing power density requirements, partial discharge (PD) starts becoming a threat that can cause insulation breakdown, if not checked. For high voltage applications, PD awareness is particularly important, and this paper describes how various trace shapes play a critical role in the electrical reliability of modules with regard to electrical breakdown. Sharp corners of traces must be avoided, as is generally done for mechanical stability reasons, by filleting the corners. High voltage experiments were performed to confirm the detrimental electrical effects of sharp corners. The degree of improvement by completely avoiding sharp corners was quantified for various trace gaps. Simulations were performed to predict the improvement in terms of E-field concentration with respect to the radius of fillets. Preliminary fillets were implemented in a stand-alone in-house tool called PowerSynth, which is used for electrical and thermal optimization.",
keywords = "charge density, electric field, electrical breakdown, hi-pot, high voltage, layout, Maxwell, partial discharge, power module, PowerSynth",
author = "Shilpi Mukherjee and Tristan Evans and Balaji Narayanasamy and Quang Le and Emon, \{Asif Imran\} and Amol Deshpande and Fang Luo and Yarui Peng and Steve Pytel and Tom Vrotsos and Alan Mantooth",
note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 19th IEEE Workshop on Control and Modeling for Power Electronics, COMPEL 2018 ; Conference date: 25-06-2018 Through 28-06-2018",
year = "2018",
month = sep,
day = "10",
doi = "10.1109/COMPEL.2018.8459973",
language = "English",
isbn = "9781538655412",
series = "2018 IEEE 19th Workshop on Control and Modeling for Power Electronics, COMPEL 2018",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2018 IEEE 19th Workshop on Control and Modeling for Power Electronics, COMPEL 2018",
}