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Ultra-low spike rate silicon neuron

  • University of Maryland, College Park

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

We present theory, design and simulation results for a silicon neuron circuit that achieves extremely low spike rates and small footprint by exploiting the low current characteristics in floating gate structures. As in biological counterparts, the spike rate is compressed against stimulant current. Simulations confirm sub-Hertz spike rates in steady state with a stimulant current of 7pA and below, and up to 100x spike rate reduction at 1nA. With reasonable device variation modelling, Monte Carlo simulation shows that spike rate varies by a standard deviation of 25%.

Original languageEnglish
Title of host publicationConference Proceedings - IEEE Biomedical Circuits and Systems Conference Healthcare Technology, BiOCAS2007
Pages95-98
Number of pages4
DOIs
StatePublished - 2007
EventIEEE Biomedical Circuits and Systems Conference Healthcare Technology, BiOCAS2007 - Montreal, QC, Canada
Duration: Nov 27 2007Nov 30 2007

Publication series

NameConference Proceedings - IEEE Biomedical Circuits and Systems Conference Healthcare Technology, BiOCAS2007

Conference

ConferenceIEEE Biomedical Circuits and Systems Conference Healthcare Technology, BiOCAS2007
Country/TerritoryCanada
CityMontreal, QC
Period11/27/0711/30/07

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