Using a Symbolic Knowledge Graph to Address LLM Limitations in Analog Circuit Topology Generation

Analog circuit topology synthesis has been shown to be hard arguably due to the difficulty to formulate it either as a regression or as an optimization problem, which are currently the two main synthesis approaches. This paper proposes a novel analog circuit topology synthesis methodology that combines the capabilities of Deep Neural Models with the advantages of symbolic representations. It integrates Large Language Models (LLMs) with Symbolic Knowledge Graphs (SKGs): an LLM offers broad descriptions of the topological modules that can be incorporated into the final schematics, and an SKG incorporates all design details needed to complete the topological modules and other related circuitry of a circuit schematics. The SKG also supports the causal reasoning flow through which the modules indicated by the LLM are selected and integrated with each other.